The project of Sh-RISC

The Sh-RISC is a project about to implement a workable RISC microprocessor by AHDL, VHDL. 

The project began in spring 2002 and it is held by a student who graduated from Si-Hai vocational college. 
The goal of the project is to develop and implement a superscalar RISC microprocessor. 
For some reasons, the project, by now, is still under construction. There are many technical issues needed to evaluate. 
This blog will try to provide more details about the schedule of development and the information of the microprocessor. 
I hope all of you enjoy the achievement of what I have done. 
I will upload the core as soon as possible if nothing goes wrong. 
Moreover, I do really want to meet some volunteers who are good at programming VHDL and C, designing RISC architecture.

Good luck for me.
wish you have a nice day.

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